Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
Format
Post in Engineering
BY Katarzyna Radecka, Zeljko Zilic
Shared By Guest
This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. The Author of this Book is Katarzyna Radecka, Zeljko Zilic It brings the results in the direction of merging manufacturing test vector generation and verification. Array ISBN . . Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing) available in English.
Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
You should be logged in to Download this Document. Membership is Required. Register here
Related Books on Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
- Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
- Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault (Frontiers in Electronic Testing)
- Hardware and Software, Verification and Testing: First International Haifa Verification Conference, Haifa, Israel, November 13-16, 2005, Revised ... / Programming and Software Engineering)
Comments (0)